1. Field of the Invention
The present invention relates to a semiconductor device and an electronic device and a technology effectively applied to, for example, a semiconductor device that has a plurality of semiconductor chips, each of which has a transistor formed therein, in a package and has a high breakdown voltage.
2. Description of the Related Art
As one of the semiconductor devices has been known a semiconductor device having a structure (so-called SOP8 type) in which two semiconductor chips each having a transistor formed therein is mounted in a package and in which four leads are protruded from each side of one pair of sides opposite to each other of the package (for example, JPA-2000-217416).
A plurality of power MOS FETs are used for a motor control, a power supply, and the like. A composite power MOS FET (transistor) studied by the inventors includes two power MOS FETs. FIGS. 21 to 24 are illustrations related to a conventional semiconductor device 80 in which two power MOS FETs (transistors) are packaged in a single package.
The semiconductor device 80, as shown in a schematic plan view in FIG. 21 and in a schematic sectional view in FIG. 23, outwardly, has a structure in which four leads 82 are protruded in a gullwing shape from each side of one pair of sides (long sides) opposite to each other of a flat and square package 81. In FIG. 21, the leads 82 are denoted by reference numerals from 1 to 8 as lead terminal numbers. These reference numerals are thought to be arranged anticlockwise along the periphery of the package. That is, a shown in FIG. 21, the leads 82 are denoted along the lower side of the package 81 from the left to the right by the reference numerals 1 to 4 and are denoted along the upper side from the right to the left by the reference numerals 5 to 8.
For example, a lead located at a lead terminal 1 is a source electrode terminal (S1). Similarly, a lead terminal 2 is a gate electrode terminal (G1) and lead terminals 8 and 7 are drain electrode terminals (D1) and construct, for example, the terminals of a switching transistor, respectively. Further, a lead terminal 3 is a source electrode terminal (S2) and a lead terminal 4 is a gate electrode terminal (G2) and lead terminals 6, 5 are drain terminals (D2) and construct, for example, the terminals of a rectifier transistor. Here, the arrangement of the lead terminal numbers is the same also in the description of the invention.
FIG. 22 is a schematic plan view to show in a transparent state a semiconductor chip fixing part, a semiconductor chip and leads in the package 81. As shown in FIG. 22, the leads 82 of the lead terminals 8, 7 are formed in a structure in which they are coupled to a semiconductor chip fixing part 85 located in the package 81 and shaped like a square. Further, the lead terminals 1, 2 opposite to the lead terminals 8, 7 are formed independently of each other. The tip, that is, the inner end of the independent lead 82 is formed into a wire bonding pad 86 having a wide width so as to enable wire bonding. A semiconductor chip 90 is fixed via a conductive adhesive 87 to the top surface of the semiconductor chip fixing part 85 (see FIG. 23). This semiconductor chip 90 has a vertically structured power MOSFET formed therein and has a gate electrode pad 91 and a source electrode pad 92 formed on its top surface and has a drain electrode formed on its bottom surface. Hence, the semiconductor chip 90 is fixed to the semiconductor chip fixing part 85 with the conductive adhesive 87, whereby the leads 82 of the lead terminals 8, 7 construct drain terminals (D1). The wire bonding pad 86 of the lead terminal 1 and the source electrode pad 92 of the semiconductor chip 90 are electrically connected to each other by a plurality of conductive wires 93. The wire bonding pad 86 of the lead terminal 2 and the gate electrode pad 91 of the semiconductor chip 90 are electrically connected to each other by a conductive wire 93. In this manner, a switching transistor is formed.
Further, similarly, as shown in FIG. 22, the leads 82 of the lead terminals 6, 5 are formed in a structure in which they are coupled to a semiconductor chip fixing part 95 located in the package 81 and shaped like a square. Further, the lead terminals 3, 4 opposite to the lead terminals 6, 5 are formed independently of each other. The tip, that is, the inner end of the independent lead 82 is formed into a wire bonding pad 86 having a wide width so as to enable wire bonding. A semiconductor chip 96 is fixed via a conductive adhesive (not shown) to the top surface of the semiconductor chip fixing part 95. This semiconductor chip 96 has a vertically structured power MOSFET formed therein and has a gate electrode pad 97 and a source electrode pad 98 formed on its top surface and has a drain electrode formed on its bottom surface. Hence, the semiconductor chip 90 is fixed to the semiconductor chip fixing part 95 with the conductive adhesive, whereby the leads 82 of the lead terminals 6, 5 construct drain terminals (D2). The wire bonding pad 86 of the lead terminal 3 and the source electrode pad 98 of the semiconductor chip 96 are electrically connected to each other by a plurality of conductive wires 93. The wire bonding pad 86 of the lead terminal 4 and the gate electrode pad 97 of the semiconductor chip 90 are electrically connected to each other by a conductive wire 93. In this manner, a rectifier transistor is formed.
The semiconductor 80 like this, shown in FIG. 24, is mounted on a mounting board 100. That is, the mounting portions at the tips of the leads 82 protruding from both sides of the package 81 are mounted via an adhesive such as solder (not shown) to respective lands 101 formed on the top surface of the mounting board 100.
For example, the width a of a lead is 0.4 mm, the pitch b of the lead is 1.27 mm, a gap c between the leads is 0.87 mm, the width f of a land is 0.76 mm, a gap g between the lands is 0.51 mm.
In this kind of semiconductor device in current use, a breakdown voltage is as low as, for example, 250 V or less and mainly of 30 V class. On the other hand, depending on a field where a semiconductor device is used, a semiconductor device having a higher breakdown voltage is desired. For example, the above-described semiconductor device mounted with two transistor chips is required to have a breakdown voltage as high as 600 V. However, in now-available products, a gap between neighboring leads is as narrow as 0.87 mm and it turned out that the increasing of the breakdown voltage of the product results in increasing a potential that a short circuit might develop between the leads of neighboring transistors and hence in making it impossible to provide a high breakdown voltage by the present structure.
According to the studies by the inventor, it turned out that in the package, the respective leads are covered with resin, which is a main constituent material of the package, and hence can secure a comparatively high breakdown voltage but that in the portions where leads protrude from the package (side portions of the package), a discharge phenomenon develops between the neighboring leads to cause a short circuit between the leads as a result.